The invention relates to a process for producing an integrated semiconductor memory configuration.
Semiconductor-based memory configurations usually comprise a number of memory cells which each have a selection transistor and a storage capacitor connected to the selection transistor. During a production process for such semiconductor memory configurations, it is usual to apply first electrodes over conductive connections, a respective one of the conductive connections connecting one of the first electrodes to a respective one of the selection transistors. A storage dielectric is applied over the first electrode and in turn has a second electrode applied to it, so that the first and the second electrode as well as the intermediate storage dielectric form a storage capacitor which is conductively connected to one of the selection transistors.
The use of new types of ferroelectric materials as the storage dielectric for storage capacitors allows semiconductor memories to be produced that do not lose their information (stored in the form of electric charge) after a supply voltage failure, and whose memory contents do not have to be refreshed at regular intervals as a result of leakage currents.
A critical factor for the use of most of the previously known ferroelectric materials of this type is their processing within a semiconductor process. Most ferroelectric materials of this type are deposited at high temperatures in an atmosphere containing oxygen. The use of such ferroelectric materials in the process described above, in which the storage dielectric is applied over the first electrode, which in turn is situated above a conductive connection to one of the selection transistors, results in oxidation of the conductive connection because, during deposition of the ferroelectric materials, oxygen diffuses through the first electrode in the direction of the conductive connection and oxidizes the latter. Oxidation of the conductive connection interrupts the electrical connection between the storage capacitor and the selection transistor of a memory cell, with the result being that the latter is no longer functional.
Solutions for preventing oxidation of the conductive connection during deposition of a ferroelectric storage dielectric call for applying barrier layers between the conductive connection and the first electrode, in which case the barrier layers have to be electrically conductive but capable of resisting oxidation and diffusion of oxygen. A disadvantage of the use of barrier layers is that it is hard to find suitable materials that are electrically conductive, impermeable to oxygen, capable of resisting oxidation and that can be suitably applied to the conductive connections.
A process for producing an integrated semiconductor memory configuration having a ferroelectric storage dielectric without using barrier layers is described in U.S. Pat. No. 5,439,840. In this described process, the first electrodes, the storage dielectric and the second electrode are applied over an insulation layer which is situated above selection transistors, using deposition processes. Subsequently, contact holes extending to the selection transistors are produced through the second electrode, the storage dielectric, the first electrode and the insulation layer and can be used to make electrical contact between the second electrode and the selection transistor. The particular disadvantage of this is the complex application of a further insulation layer in the contact hole in order to provide electrical insulation between the first electrode and the second electrode.
It is accordingly an object of the present invention to provide a process for producing an integrated semiconductor memory configuration, in which ferroelectric materials are used to produce storage dielectrics for storage capacitors, and in which the use of barrier layers between the conductive connection and the first electrode can be dispensed with, so that the above-mentioned disadvantages do not arise.
With the foregoing and other objects in view there is provided, in accordance with the invention, a first embodiment of a process for producing an integrated semiconductor memory configuration, which comprises:
providing a configuration of selection transistors having source regions and an insulation layer formed with contact holes extending through to the source regions;
subsequently providing first contact plugs in the contact holes;
subsequently applying at least one first electrode on a surface of the insulation layer; and forming the first electrode with cutouts exposing surfaces of the first contact plugs and regions of the surface of the insulation layer adjacent the contact holes;
subsequently depositing a dielectric layer on the surfaces of the first contact plugs, the regions of the surface of the insulation layer adjacent the contact holes, and the first electrode;
subsequently depositing a second layer of electrode material on the dielectric layer;
subsequently separating the second layer of electrode material into sections to produce second electrodes;
subsequently exposing the surfaces of the first contact plugs; and
subsequently producing second contact plugs above the exposed first contact plugs electrically connecting a respective one of the second electrodes to a respective one of the first contact plugs.
With the foregoing and other objects in view there is provided, in accordance with the invention, a second embodiment of a process for producing an integrated semiconductor memory configuration, which comprises:
providing a configuration of selection transistors having source regions and an insulation layer formed with contact holes extending through to the source regions;
subsequently providing first contact plugs in the contact holes;
subsequently applying at least one first electrode on a surface of the insulation layer; and forming the first electrode with cutouts exposing surfaces of the first contact plugs and regions of the surface of the insulation layer adjacent the contact holes;
subsequently depositing a dielectric layer on the surfaces of the first contact plugs, the regions of the surface of the insulation layer adjacent the contact holes, and the first electrode;
subsequently exposing the surfaces of the first contact plugs;
subsequently depositing a second layer of electrode material on the exposed surfaces of the first contact plugs and on the dielectric layer; and
subsequently separating the second layer of electrode material into sections to produce second electrodes.
In accordance with an added feature of the invention, the first electrode application step is performed by depositing a layer of electrode material; and the step of forming cutouts is performed by removing the layer of electrode material from the surfaces of the first contact plugs and regions of the surface of the insulation layer adjacent the contact holes.
In accordance with an additional feature of the invention, before the first electrode application step, a structured auxiliary layer is applied on the surface of the insulation layer; and the structured auxiliary layer is formed with cutouts exposing surfaces of the first contact plugs and regions of the surface of the insulation layer adjacent the contact holes.
In accordance with an another feature of the invention, a material having ferroelectric properties is selected as the dielectric layer.
In accordance with a further feature of the invention, a material having ferroelectric properties is selected as the dielectric layer.
In accordance with another added feature of the invention, a material having a dielectric constant greater than 10 is selected as the dielectric layer.
In accordance with another additional feature of the invention, a an oxide-containing material selected from the group consisting of SrBi2(Ta1xe2x88x92xNbx)2O9, Pb(Zr, Ti)O3, (Ba, Sr)TiO3, and SrTiO3 is selected as the dielectric layer.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a first embodiment of an integrated semiconductor memory configuration comprising:
a plurality of identical memory cells each including:
a selection transistor having a source region;
an insulation layer having a surface and being disposed above the selection transistor; the insulation layer having a contact hole formed therein above the source region of the selection transistor;
a first contact plug disposed in the contact hole and being conductively connected to the source region;
a first electrode disposed on the surface of the insulation layer;
a dielectric layer disposed on the first electrode;
a second electrode disposed on the dielectric layer and being electrically isolated from the first electrode by the dielectric layer; and
a second contact plug electrically connecting the second electrode to the first contact plug and being electrically isolated from the first electrode by a portion of the dielectric layer.
In accordance with an added mode of the invention, a structured auxiliary layer is disposed between the surface of the insulation layer and the first electrode; the auxiliary layer being formed with a cutout disposed above the contact hole and above regions of the surface of the insulation layer adjacent the cutout.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a second embodiment of an integrated semiconductor memory configuration comprising:
a plurality of identical memory cells each including:
a selection transistor having a source region;
an insulation layer having a surface and being disposed above the selection transistor; the insulation layer having a contact hole formed therein above the source region of the selection transistor;
a first contact plug disposed in the contact hole and being conductively connected to the source region;
a structured auxiliary layer disposed on the surface of the insulation layer; the auxiliary layer being formed with a cutout disposed above the contact hole and above regions of the surface of the insulation layer adjacent the cutout;
a first electrode disposed on the structured auxiliary layer;
a dielectric layer disposed on the first electrode;
a second electrode disposed on the dielectric layer and being electrically isolated from the first electrode by the dielectric layer; and
a second contact plug electrically connecting the second electrode to the first contact plug and being electrically isolated from the first electrode by a portion of the dielectric layer.
In accordance with an additional mode of the invention, the second contact plug is an integral part of the second electrode.
In accordance with another mode of the invention, the dielectric layer is a material having ferroelectric properties.
In accordance with a further mode of the invention, the dielectric layer is a material having a dielectric constant greater than 10.
In accordance with a concomitant mode of the invention, the dielectric layer is an oxide-containing material selected from the group consisting of SrBi2(Ta1xe2x88x92xNbx)2O9, Pb(Zr, Ti)O3, (Ba, Sr)TiO3, and SrTiO3.
In the inventive process for producing an integrated semiconductor memory configuration, a conductive connection is produced between one of the two electrodes, in this example, the second electrode, and the selection transistor only after the storage dielectric has been deposited. The conductive connection between the source region of the selection transistor and the second electrode is produced above the first and the second contact plug in the present invention. Oxidation of surfaces of the first contact plugs is acceptable when the dielectric layer is being deposited. This is because in one of the next process steps, when the first contact plugs are exposed and before the second contact plugs are produced, oxidized regions of the surfaces of the first contact plugs can be removed. The process is suitable with use of any desired dielectric as the storage dielectrics in storage capacitors in integrated semiconductor memory configurations. It is particularly suitable with use of ferroelectric materials as storage dielectrics, because in this process the above-mentioned problems, such as oxidation of the conductive connection to the selection transistors during deposition of the storage dielectric, cannot arise, since the conductive connection is not produced until after the storage dielectric has been deposited. In addition, the process is simple to carry out with previously known processes for producing integrated semiconductor memory configurations.
There are various conceivable processes for producing the first electrodes above the first main surface of the insulation layer. One embodiment of the invention enables production of the first electrodes by depositing a first layer of electrode material in the direction of the first main surface. The first layer is subsequently removed, preferably by anisotropic etching, from the top surfaces of the first contact plugs that are situated in the first main surface and from regions of the first main surface that are adjacent to the top surfaces of the first contact plugs. Cutouts in the first layer are thereby produced with areas that are larger than the top surfaces of the first contact plugs. In the semiconductor memory configuration produced using the process a dielectric layer is deposited in a following process step. Parts of the dielectric layer that are situated on the exposed regions of the first main surface isolate the second contact plugs which are electrically connected to the second electrode, from the first electrode.
A further embodiment of the invention enables production of the first layer by depositing electrode material on an auxiliary layer that is structured to have cutouts above the first contact plugs. The cutouts expose the surfaces of the first contact plugs as well as adjacent regions of the first main surface. After the first layer of electrode material has been deposited, the first layer is removed from the surfaces of the first contact plugs and adjacent regions of the first main surface. The application of the first electrodes over the auxiliary layer causes an increase in the surface area of the first electrode. This is because the first electrode also extends over lateral surfaces of the cutouts in the auxiliary layer in addition to surfaces of the auxiliary layer which run parallel to the first main surface. An increase in the surface area of the first electrode increases the capacitor surface area of the produced storage capacitors, and thus increases the storage capacity.
A further embodiment of the invention provides for the surfaces of the first contact plugs to be exposed right after the dielectric layer has been deposited and before the second layer of electrode material is deposited, and for any oxidized regions of the first contact plugs to be removed. This process provides the advantage that, in one of the next process steps, the second layer of electrode material can be applied directly over the first contact plugs, so that there is no need to produce a second contact plug. This process is particularly suitable if, after the dielectric layer has been deposited, there are no other required process steps in which the first contact plugs could be oxidized.
The ferroelectric properties of most of the previously known ferroelectric materials that may be used as the storage dielectric in one embodiment of the invention are temperature-dependent. These ferroelectric materials have a ferroelectric behavior below a characteristic or particular temperature, whereas they behave paraelectrically above this characteristic or particular temperature. The dielectric constant in the paraelectric state is considerably higher than the dielectric constants of previously used storage dielectrics. The temperature below which ferroelectric properties are established is very low for some ferroelectric materials, so that, from a technical point of view, these ferroelectric materials are always used in the paraelectric state. The dielectric constant of a selected ferroelectric material in the paraelectric state is above 10, and is preferably above 100.
One feature of the invention provides for the storage dielectrics used to be materials whose dielectric constant is higher than 10. Such materials may be the above-mentioned ferroelectric materials, for example, which are used above their characteristic temperature.
One feature of the invention provides for an oxide-containing dielectric to be used as storage dielectrics. The class of these substances includes, for example, SBTN SrBi2(Ta1xe2x88x92xNbx)2O9, PZT Pb(Zr, Ti)O3, BST (Ba, Sr)TiO3 and ST SrTiO3. The formula Pb(Zr, Ti)O3 represents PbZrxTi1xe2x88x92xO3. The proportion of Zr and Ti in this substrate can vary. The ratio of Zr and Ti is a definitive determining factor for the temperature response of this dielectric, i.e. determining the temperature below which the substrate has ferroelectric properties and above which the substrate has paraelectric properties. The formula (Ba, Sr)TiO3 represents BaxSr1xe2x88x92xTiO3, and the temperature response for this substrate may be definitively determined by the ratio of Ba to Sr. The list of these substances is by no means complete. The selection of one of the substances as a storage dielectric depends ultimately on processing factors during the production process, but also on factors during the use of the semiconductor memory configuration, for example the ambient temperature.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a process for producing an integrated semiconductor memory configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.